Low-density parity-check (LDPC) is a type of error correction coding (ECC) mechanism that can be performed by a storage device. LDPC ECC engines often support a soft bit page read mode. In the soft bit page read mode, data is read from a page of memory that stores ECC parity information. The LDPC ECC engine may request a soft bit page read if the data read from the page is expected to be erroneous. During the soft bit page read, data from the page is sensed using an additional set of threshold voltages. The sensed data may then be “toggled out” (e.g., transferred) from the memory to the LDPC ECC engine. The soft bit page read operation may provide the LDPC ECC engine with an indication as to which memory cells have a high probability of being erroneous. Such information may improve decoding performance of the LDPC ECC engine. However, performing the additional sensing and toggle operations for the soft bit page read may decrease overall throughput at the storage device. This performance impact may particularly affect systems that use a low frequency/bandwidth bus between the memory and the LDPC ECC engine.